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| FUJITSU SEMICONDUCTOR DATA SHEET DS05-20908-2E FLASH MEMORY CMOS 32 M (4 M x 8/2 M x 16) BIT Dual Operation MBM29DL34TF/BF 70 s DESCRIPTION The MBM29DL34TF/BF are a 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. Power Supply Voltage (V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MBM29DL34TF/BF 70 2.7 V to 3.6 V 70 70 30 s PACKAGES 48-pin plastic TSOP (1) Marking side 48-ball plastic FBGA (FPT-48P-M19) (BGA-48P-M12) MBM29DL34TF/BF70 ) (Continued) MBM29DL34TF/BF are organized into two physical banks; Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu's standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. In the device, a design concept called Sliding Bank Architecture is implemented. Using this concept the device can execute simultaneous operation between Bank 1 and Bank 2(Refer to "1. Simultaneous Operation" in "s FUNCTIONAL DESCRIPTION".). The standard device offers access times 70 ns allowing operation of high-speed microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) and output enable (OE) controls. The MBM29DL34TF/BF support pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies the proper cell margin. Each sector is typically erased and verified in 0.5 second (if already completely preprogrammed) . The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the device internally return to the read mode. The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the Embedded ProgramTM * Algorithm or Embedded EraseTM * Algorithm, the device is automatically reset to the read mode and have erroneous data stored in the address locations being programmed or erased. These locations need rewriting after the Reset. Resetting the device enables the system's microprocessor to read the boot-up firmware from the Flash memory. Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/ word at a time using the EPROM programming mechanism of hot electron injection. *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MBM29DL34TF/BF70 s FEATURES * 0.17 m Process Technology * Simultaneous Read/Write Operations (Dual Bank) Bank 1 : 8 Mbit Bank 2 : 24 Mbit Host system can program or erase in one bank, then immediately and simultaneously read and from the other bank. Zero latency between read and write operation. Read - while - erase Read - while - program * Single 3.0 V Read, Program, and Erase Minimizes system level power requirements * Compatible with JEDEC-standard Commands Uses same software commands as E2PROMs * Compatible with JEDEC-standard World-wide Pinouts 48-pin TSOP (1) (Package suffix : TN - Normal Bend Type, TR - Reversed Bend Type) 48-ball FBGA (Package suffix : PBT) * Minimum 100,000 Program/Erase Cycles * High Performance 70 ns maximum access time * Sector Erase Architecture Eight 4 K word and sixty-three 32 K word sectors in word mode Eight 8 K byte and sixty-three 64 K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture T = Top sector B = Bottom sector * HiddenROM Region 256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC Input Pin At VIL, allows protection of "outermost" 2 x 8 bytes on boot sectors, regardless of sector protection/unprotection status. At VIH, allows removal of boot sector protection At VACC, increases program performance * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device (Continued) 3 MBM29DL34TF/BF70 (Continued) * Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations * Sector Group Protection Set function by Extended sector group protection command * Fast Programming Function by Extended Command * Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin. * In accordance with CFI (Common Flash Memory Interface) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. Bank and Sector Organization Table Device Part Number MBM29DL34TF MBM29DL34BF Bank 1 Bank A (SA70 to 48) Bank A (SA0 to 22) Bank 2 Bank B (SA47 to 0) Bank B (SA23 to 70) 4 MBM29DL34TF/BF70 s PIN ASSIGNMENTS TSOP (1) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 Normal Bend (FPT-48P-M19) (Continued) 5 MBM29DL34TF/BF70 (Continued) FBGA (TOP VIEW) Marking side A6 A13 A5 A9 A4 WE A3 B6 A12 B5 A8 B4 RESET B3 C6 A14 C5 A10 C4 N.C. C3 A18 C2 A6 C1 A2 D6 A15 D5 A11 D4 A19 D3 A20 D2 A5 D1 A1 E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0 F6 G6 H6 VSS H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS BYTE DQ15/A-1 F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE RY/BY WP/ACC A2 A7 A1 A3 B2 A17 B1 A4 (BGA-48P-M12) 6 MBM29DL34TF/BF70 s PIN DESCRIPTION Pin A20 to A0, A-1 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE WP/ACC VCC VSS N.C. Address Input Data Input/Output Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Selects Byte (8-bit) or Word (16-bit) mode Hardware Write Protection/Program Acceleration Device Power Supply Device Ground No Internal Connection Function s LOGIC SYMBOL A-1 21 A20 to A0 DQ15 to DQ0 CE OE WE RESET BYTE WP/ACC RY/BY 16 or 8 7 MBM29DL34TF/BF70 s BLOCK DIAGRAM VCC VSS Bank 2 Address A20 to A0 (A-1) Cell Matrix (Bank 2) X-Decoder RY/BY State Control & Command Register Status Control DQ15 to DQ0 RESET WE CE OE BYTE WP/ACC DQ15 to DQ0 X-Decoder Y-Gating & Data Latch Bank 1 Address Cell Matrix (Bank 1) 8 Y-Gating & Data Latch MBM29DL34TF/BF70 s DEVICE BUS OPERATION MBM29DL34TF/BF User Bus Operations Table (Word Mode : BYTE = VIH) Operation Standby Autoselect Manufacturer Code *1 Autoselect Device Code *1 Extended Auto-Select Device Code *1 Read * 3 CE OE WE H L L L L L L L L L X X X X L L L L L H H VID L X X X X H H H H H H L L H X X X A0 X L H L H A0 X A0 L L X X X A1 X L L H H A1 X A1 H H X X X A2 X L L H H A2 X A2 L L X X X A3 X L L H H A3 X A3 L L X X X A6 X L L L L A6 X A6 L L X X X A9 X VID VID VID VID A9 X A9 VID VID X X X DQ15 to DQ0 High-Z Code Code Code Code DOUT High-Z DIN X Code X High-Z X RESET H H H H H H H H H H VID L X WP/ ACC X X X X X X X X X X X X L Output Disable Write (Program/Erase) Enable Sector Group Protection *2, *4 Verify Sector Group Protection *2, *4 Temporary Sector Group Unprotection *5 Reset (Hardware) Boot Block Sector Write Protection Legend : L = VIL, H = VIH, X = VIL or VIH, See "s DC CHARACTERISTICS" for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29DL34TF/BF Command Definitions Table". *2: Refer to section on "8. Sector Group Protection" in s FUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 2.7 V to 3.6 V *5: Also used for extended sector group protection. 9 MBM29DL34TF/BF70 MBM29DL34TF/BF User Bus Operations Table (Byte Mode : BYTE = VIL) Operation Standby Autoselect Manufacturer Code *1 Autoselect Device Code *1 Extended Auto-Select Device Code *1 Read * 3 CE OE WE H L L L L L L L L L X X X X L L L L L H H VID L X X X X H H H H H H L L H X X X DQ15 /A-1 X L L L L A-1 X A-1 L L X X X A0 X L H L H A0 X A0 L L X X X A1 X L L H H A1 X A1 H H X X X A2 X L L H H A2 X A2 L L X X X A3 X L L H H A3 X A3 L L X X X A6 X L L L L A6 X A6 L L X X X A9 DQ7 to DQ0 RESET X VID VID VID VID A9 X A9 VID VID X X X High-Z Code Code Code Code DOUT High-Z DIN X Code X High-Z X H H H H H H H H H H VID L X WP/ ACC X X X X X X X X X X X X L Output Disable Write (Program/Erase) Enable Sector Group Protection *2, *4 Verify Sector Group Protection *2, *4 Temporary Sector Group Unprotection *5 Reset (Hardware) Boot Block Sector Write Protection Legend : L = VIL, H = VIH, X = VIL or VIH, See "s DC CHARACTERISTICS" for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29DL34TF/BF Command Definitions Table". *2: Refer to section on "8. Sector Group Protection" in s FUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 2.7 V to 3.6 V *5: Also used for extended sector group protection. 10 MBM29DL34TF/BF70 MBM29DL34TF/BF Command Definitions Table *1 Command sequence Word Byte Word Byte Word 4 Byte Word Byte 4 1 1 6 6 1 1 3 2 2 AAAh 555h AAAh BA BA 555h AAAh 555h AAAh BA BA 555h AAAh XXXh XXXh BA BA AAh B0h 30h AAh AAh B0h 30h AAh A0h 90h Bus write cycles req'd First bus write cycle Second bus write cycle Third bus write cycle Addr. 555h AAAh (BA) 555h (BA) AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh Fourth bus Fifth bus Sixth bus read/write write cycle write cycle cycle Addr. Data Addr. Data XXXh F0h 555h AAAh 555h AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h PA XXXh XXXh 55h 55h 55h 55h PD 00h*11 AAh 2AAh 555h 2AAh 55h 55h Data Addr. Data Addr. Data Addr. Data F0h RA RD Reset *2 Reset *2 1 3 Autoselect (Device ID) 90h 00h 04h Program A0h 80h 80h 20h PA 555h AAAh 555h AAAh PD AAh AAh 2AAh 555h 2AAh 555h 55h 55h 555h AAAh SA 10h 30h Program Suspend Program Resume Chip Erase Sector Erase Word Byte Word Byte 3 Erase Suspend *3 Erase Resume * Set to Fast Mode Fast Program *4 Word Byte Word Byte Word Reset from 5 Fast Mode * Byte Extended Word Sector Group Protection Byte *6,*7 Word Query *8 Byte HiddenROM Entry *9 Word Byte 4 XXXh 60h SGA 60h SGA 40h SGA SD 1 (BA) 55h (BA) AAh 555h AAAh 98h 3 AAh 2AAh 555h 55h 555h AAAh 88h (Continued) 11 MBM29DL34TF/BF70 (Continued) Command sequence HiddenRom Program *10 HiddenRom Exit *10 Word Byte Word 4 Byte AAAh Bus write cycles req'd First bus write cycle Second bus write cycle Third bus write cycle Addr. 555h AAAh (HRBA) 555h (HRBA) AAAh Data A0h Fourth bus read/write cycle Addr. (HRA) PA Fifth bus Sixth bus write cycle write cycle Addr. Data Addr. Data 555h AAAh 555h AAh 555h AAh 2AAh 555h 2AAh 55h 55h Data Addr. Data Addr. Data PD 4 90h XXXh 00h *1 : The command combinations not described in "MBM29DL34TF/BF Command Definitions Table" are illegal. *2 : Both of these reset commands are equivalent. *3 : Erase Suspend and Erase Resume command are valid only during a sector erase operation. *4 : This command is valid during Fast Mode. *5 : The Reset from Fast Mode command is required to return to the read mode when the device is in Fast Mode. *6 : This command is valid while RESET = VID (except during HiddenROM mode). *7 : Sector Group Address (SGA) with (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) . *8 : The valid address are A6 to A0. *9 : The HiddenROM Entry command is required prior to the HiddenROM programming. *10 : This command is valid during HiddenROM mode. *11 : The date "F0h" is also acceptable. Notes: * Address bits A20 to A11 = X = "H" or "L" for all address commands except or Program Address (PA) , Sector Address (SA) , Bank Address (BA) . * Bus operations are defined in "MBM29DL34TF/BF User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" (s DEVICE BUS OPERATION). * RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A20 to A18) * RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. * SGA = Sector Group Address. The combination of A20 to A12 will uniquely select any sector group. SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. * HRA = Address of the HiddenROM area 29DL34TF (Top Boot Type) Word Mode : 1FF000h to 1FF07Fh Byte Mode : 3FE000h to 3FE0FFh 29DL34BF (Bottom Boot Type) Word Mode : 000000h to 00007Fh Byte Mode : 000000h to 0000FFh * HRBA = Bank Address of the HiddenROM area 29DL34TF (Top Boot Type) : A20 = A19 = A18 = 1 29DL34BF (Bottom Boot Type) : A20 = A19 = A18 = 0 * The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1 * Both Reset commands are functionally equivalent, resetting the device to the read mode. 12 MBM29DL34TF/BF70 MBM29DL34TF Sector Group Protection Verify Autoselect Codes Table A6 A3 A2 A1 A0 A20 to A12 A-1*1 BA* 3 Type Code (HEX) 04h 50h 2250h 01h*2 Manufacture's Code Device Code Byte Word VIL VIL VIL VIL VIL VIL VIL VIL VIL VIH VIL VIL X VIL BA*3 Sector Group Addresses Sector Group Protection VIL VIL VIL VIH VIL *1 : A-1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. MBM29DL34TF Extended Autoselect Code Table Type Manufacture's Code Device Code Byte* Code 04h DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 A-1/0 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 HZ 0 0 0 HZ 1 0 0 HZ 0 0 0 HZ 0 0 0 HZ 0 0 0 HZ 1 0 0 HZ 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 50Eh A-1 0 A-1/0 Word 2250Eh 01h Sector Group Protection HZ: High-Z * : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address. 13 MBM29DL34TF/BF70 MBM29DL34BF Sector Group Protection Verify Autoselect Codes Table A6 A3 A2 A1 A0 A20 to A12 A-1*1 BA*3 BA*3 Sector Group Addresses VIL VIL VIL VIL VIL VIL VIL VIL VIL VIH VIL VIL X VIL Byte Word Type Code (HEX) 04h 53h 2253h 01h*2 Manufacture's Code Device Code Sector Group Protection VIL VIL VIL VIH VIL *1 : A-1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. MBM29DL34BF Extended Autoselect Code Table Type Manufacture's Code Device Code Byte* Word Code 04h 53h 2253h 01h DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 A-1/0 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 HZ 0 0 0 HZ 1 0 0 HZ 0 0 0 HZ 0 0 0 HZ 0 0 0 HZ 1 0 0 HZ 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 1 A-1 0 A-1/0 Sector Group Protection HZ: High-Z * : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A-1, the lowest address. 14 MBM29DL34TF/BF70 s SECTOR-ERASE ARCHITECTURE Sector Address Table (MBM29DL34TF) Sector address Sector size (x8) x Bank address (Kbytes/ Address range A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) x Address range Bank Sector A20 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 Bank 2 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 000000h to 00FFFFh 000000h to 007FFFh 010000h to 01FFFFh 008000h to 00FFFFh 020000h to 02FFFFh 010000h to 017FFFh 030000h to 03FFFFh 018000h to 01FFFFh 040000h to 04FFFFh 020000h to 027FFFh 050000h to 05FFFFh 028000h to 02FFFFh 060000h to 06FFFFh 030000h to 037FFFh 070000h to 07FFFFh 038000h to 03FFFFh 080000h to 08FFFFh 040000h to 047FFFh 090000h to 09FFFFh 048000h to 04FFFFh 0A0000h to 0AFFFFh 050000h to 057FFFh 0B0000h to 0BFFFFh 058000h to 05FFFFh 0C0000h to 0CFFFFh 060000h to 067FFFh 0D0000h to 0DFFFFh 068000h to 06FFFFh 0E0000h to 0EFFFFh 070000h to 077FFFh 0F0000h to 0FFFFFh 078000h to 07FFFFh 100000h to 10FFFFh 080000h to 087FFFh 110000h to 11FFFFh 088000h to 08FFFFh 120000h to 12FFFFh 090000h to 097FFFh 130000h to 13FFFFh 098000h to 09FFFFh 140000h to 14FFFFh 0A0000h to 0A7FFFh 150000h to 15FFFFh 0A8000h to 0AFFFFh 160000h to 16FFFFh 0B0000h to 0B7FFFh 170000h to 17FFFFh 0B8000h to 0BFFFFh 180000h to 18FFFFh 0C0000h to 0C7FFFh 190000h to 19FFFFh 0C8000h to 0CFFFFh 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh 200000h to 20FFFFh 100000h to 107FFFh 15 MBM29DL34TF/BF70 Sector address Bank Sector SA33 SA34 SA35 SA36 SA37 SA38 SA39 Bank 2 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 Bank 1 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bank address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 (x8) x Address range (x16) x Address range 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 210000h to 21FFFFh 108000h to 10FFFFh 220000h to 22FFFFh 110000h to 117FFFh 230000h to 23FFFFh 118000h to 11FFFFh 240000h to 24FFFFh 120000h to 127FFFh 250000h to 25FFFFh 128000h to 12FFFFh 260000h to 26FFFFh 130000h to 137FFFh 270000h to 27FFFFh 138000h to 13FFFFh 280000h to 28FFFFh 140000h to 147FFFh 290000h to 29FFFFh 148000h to 14FFFFh 2A0000h to 2AFFFFh 150000h to 157FFFh 2B0000h to 2BFFFFh 158000h to 15FFFFh 2C0000h to 2CFFFFh 160000h to 167FFFh 2D0000h to 2DFFFFh 168000h to 16FFFFh 2E0000h to 2EFFFFh 170000h to 177FFFh 2F0000h to 2FFFFFh 178000h to 17FFFFh 300000h to 30FFFFh 180000h to 187FFFh 310000h to 31FFFFh 188000h to 18FFFFh 320000h to 32FFFFh 190000h to 197FFFh 330000h to 33FFFFh 198000h to 19FFFFh 340000h to 34FFFFh 1A0000h to 1A7FFFh 350000h to 35FFFFh 1A8000h to 1AFFFFh 360000h to 36FFFFh 1B0000h to 1B7FFFh 370000h to 37FFFFh 1B8000h to 1BFFFFh 380000h to 38FFFFh 1C0000h to 1C7FFFh 390000h to 39FFFFh 1C8000h to 1CFFFFh 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh (Continued) 16 MBM29DL34TF/BF70 (Continued) Sector address Bank Sector SA67 Bank 1 SA68 SA69 SA70 1 1 1 1 Bank address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector size (Kbytes/ Kwords) 8/4 8/4 8/4 8/4 (x8) x Address range (x16) x Address range 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 X X X X 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh 3FA000h to 3FBFFFh 1FD000h to 1FDFFFh 3FC000h to 3FDFFFh 1FE000h to 1FEFFFh 3FE000h to 3FFFFFh 1FF000h to 1FFFFFh Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) . The address range is A20 : A0 if in word mode (BYTE = VIH) . Sector Address Table (MBM29DL34BF) Sector address Sector size (x8) x Bank address (Kbytes/ Address range A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Bank Sector A20 (x16) x Address range SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 Bank 2 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh 390000h to 39FFFFh 1C8000h to 1CFFFFh 380000h to 38FFFFh 1C0000h to 1C7FFFh 370000h to 37FFFFh 1B8000h to 1BFFFFh 360000h to 36FFFFh 1B0000h to 1B7FFFh 350000h to 35FFFFh 1A8000h to 1AFFFFh 340000h to 34FFFFh 1A0000h to 1A7FFFh 330000h to 33FFFFh 198000h to 19FFFFh 320000h to 32FFFFh 190000h to 197FFFh 310000h to 31FFFFh 188000h to 18FFFFh 300000h to 30FFFFh 180000h to 187FFFh 2F0000h to 2FFFFFh 178000h to 17FFFFh 2E0000h to 2EFFFFh 170000h to 177FFFh 2D0000h to 2DFFFFh 168000h to 16FFFFh 2C0000h to 2CFFFFh 160000h to 167FFFh 2B0000h to 2BFFFFh 158000h to 15FFFFh 2A0000h to 2AFFFFh 150000h to 157FFFh (Continued) 17 MBM29DL34TF/BF70 Sector address Bank Sector SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 Bank 2 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 Bank 1 SA19 SA18 SA17 SA16 SA15 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) x Address range (x16) x Address range 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 290000h to 29FFFFh 148000h to 14FFFFh 280000h to 28FFFFh 140000h to 147FFFh 270000h to 27FFFFh 138000h to 13FFFFh 260000h to 26FFFFh 130000h to 137FFFh 250000h to 25FFFFh 128000h to 12FFFFh 240000h to 24FFFFh 120000h to 127FFFh 230000h to 23FFFFh 118000h to 11FFFFh 220000h to 22FFFFh 110000h to 117FFFh 210000h to 21FFFFh 108000h to 10FFFFh 200000h to 20FFFFh 100000h to 107FFFh 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 190000h to 19FFFFh 0C8000h to 0CFFFFh 180000h to 18FFFFh 0C0000h to 0C7FFFh 170000h to 17FFFFh 0B8000h to 0BFFFFh 160000h to 16FFFFh 0B0000h to 0B7FFFh 150000h to 15FFFFh 0A8000h to 0AFFFFh 140000h to 14FFFFh 0A0000h to 0A7FFFh 130000h to 13FFFFh 098000h to 09FFFFh 120000h to 12FFFFh 090000h to 097FFFh 110000h to 11FFFFh 088000h to 08FFFFh 100000h to 10FFFFh 080000h to 087FFFh 0F0000h to 0FFFFFh 078000h to 07FFFFh 0E0000h to 0EFFFFh 070000h to 077FFFh 0D0000h to 0DFFFFh 068000h to 06FFFFh 0C0000h to 0CFFFFh 060000h to 067FFFh 0B0000h to 0BFFFFh 058000h to 05FFFFh 0A0000h to 0AFFFFh 050000h to 057FFFh 090000h to 09FFFFh 048000h to 04FFFFh 080000h to 08FFFFh 040000h to 047FFFh (Continued) 18 MBM29DL34TF/BF70 (Continued) Sector address Bank Sector SA14 SA13 SA12 SA11 SA10 SA9 SA8 Bank 1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank address A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) x Address range (x16) x Address range 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 X X X X X X X 1 1 1 1 0 0 0 0 X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X 070000h to 07FFFFh 038000h to 03FFFFh 060000h to 06FFFFh 030000h to 037FFFh 050000h to 05FFFFh 028000h to 02FFFFh 040000h to 04FFFFh 020000h to 027FFFh 030000h to 03FFFFh 018000h to 01FFFFh 020000h to 02FFFFh 010000h to 017FFFh 010000h to 01FFFFh 008000h to 00FFFFh 00E000h to 00FFFFh 007000h to 007FFFh 00C000h to 00DFFFh 006000h to 006FFFh 00A000h to 00BFFFh 005000h to 005FFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) . The address range is A20 : A0 if in word mode (BYTE = VIH) . 19 MBM29DL34TF/BF70 Sector Group Addresses Table (MBM29DL34TF) A18 A17 A16 A15 A14 A13 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 X X X SA60 to SA62 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59 X X X SA1 to SA3 X X Sector group SGA0 A20 0 A19 0 A12 X Sectors SA0 20 MBM29DL34TF/BF70 Sector Group Addresses Table (MBM29DL34BF) A18 A17 A16 A15 A14 A13 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 X X X X X X X X X X X X X X 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 X X X SA70 X X X SA67 to SA69 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 X X X SA8 to SA10 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Sector group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 A20 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 A12 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 21 MBM29DL34TF/BF70 Common Flash Memory Interface Code Table Description A6 to A0 Query-unique ASCII string "QRY" Primary OEM Command Set 02h : AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VCC Max (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VPP Min voltage VPP Max voltage Typical timeout per single byte/word write 2 s N DQ15 to DQ0 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0050h 0052h 0049h 0031h 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 40h 41h 42h 43h N Typical timeout for Min size buffer write 2 s Typical timeout per individual sector erase 2 ms Typical timeout for full chip erase 2 ms Max timeout for byte/word write 2 times typical Max timeout for buffer write 2 times typical Max timeout per individual sector erase 2 times typical Max timeout for full chip erase 2 times typical Device Size = 2 byte N N N N N N N 02h : Supports x8 and x16 via BYTE with asynchronous interface. Max number of bytes in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information bit 0 to 15 : y = number of sectors bit 16 to 31 : z = size (z x 256 bytes) Erase Block Region 2 Information bit 0 to 15 : y = number of sectors bit 16 to 31 : z = size (z x 256 bytes) Query-unique ASCII string "PRI" Major version number, ASCII (Continued) 22 MBM29DL34TF/BF70 (Continued) Description Minor version number, ASCII Address Sensitive Unlock (DQ1, DQ0) 00h = Required Silicon Revision Number (DQ7 to DQ2) Erase Suspend 02h = To Read & Write Sector Protection 00h = Not Supported X = Number of sectors per group Sector Temporary Unprotection 01h = Supported Sector Protection Algorithm Dual Operation 00h = Not Supported X = Total number of sectors in all banks except Bank 1 Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported VACC (Acceleration) Supply Minimum 00h = Not Supported, DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VACC (Acceleration) Supply Maximum 00h = Not Supported, DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV Boot Type 02h = MBM29DL34BF 03h = MBM29DL34TF Program Suspend 01h = Supported Bank Organization 00h = If data at 4Ah is zero. X = Number of Banks Bank A Region Information X = Number of sectors in Bank A Bank B Region Information X = Number of sectors in Bank B Bank C Region Information X = Number of sectors in Bank C Bank D Region Information X = Number of sectors in Bank D A6 to A0 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh DQ15 to DQ0 0033h 0000h 0002h 0001h 0001h 0004h 0030h 0000h 0000h 0085h 4Eh 0095h 4Fh 50h 57h 58h 59h 5Ah 5Bh 00XXh 0001h 0004h 000Fh 0018h 0018h 0008h 23 MBM29DL34TF/BF70 s FUNCTIONAL DESCRIPTION 1. Simultaneous Operation The device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank address (A20, A19, A18) with zero latency. The device consists of the following two banks : Bank 1 : 8 x 8 KB and 63 x 64 KB; Bank 2 : 48 x 64 KB. The device can execute simultaneous operations between Bank 1 and Bank 2. The simultaneous operation cannot execute multi-function mode in the same bank. "Simultaneous Operation Table" shows the possible combinations for simultaneous operation. (Refer to "8 Bank-to-Bank Read / write Timing Diagram" in sTIMING DIAGRAM. Simultaneous Operation Table Case Bank 1 status Bank 2 status 1 2 3 4 5 6 7 Read Mode Read Mode Read Mode Read Mode Autoselect Mode Program Mode Erase Mode * Read Mode Autoselect Mode Program Mode Erase Mode * Read Mode Read Mode Read Mode * : By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. The Bank consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) means to specify each of the Banks. 2. Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current consumed is less than 5 A Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even when CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L") . Under this condition the current consumed is less than 5 A Max. Once the RESET pin is set high, the device requires tRH of wake up time for output to be valid for read access. During standby mode, the output is in the high impedance state, regardless of the OE input. 3. Automatic Sleep Mode Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in applications such as handy terminal, which requests low power consumption. To activate this mode, the devices automatically switch themselves to low power mode when the devices addresses remain stable after 150 ns from data valid. It is not necessary to control CE, WE, and OE in this mode. Under the mode, the current consumed is typically 1 A (CMOS Level) . During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are continuously read out. If the addresses are changed, the mode is automatically canceled and the devices read out the data for changed addresses. 4. Autoselect The autoselect mode allows reading out of a binary code and identifies its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be 24 MBM29DL34TF/BF70 programmed with its corresponding programming algorithm. To activate this mode, the programming equipment must force VID on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses can be either High or Low except A0, A1, A2, A3, and A6 (A-1) . (See "MBM29DL34TF/BF User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in s DEVICE BUS OPERATION.) The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "MBM29DL34TF/BF Command Definitions Table" (s DEVICE BUS OPERATION). (Refer to "2. Autoselect Command" in s COMMAND DIFINITIONS.) In Word mode, a read cycle from address 00h returns the manufacturer's code (Fujitsu = 04h) . A read cycle at address 01h outputs device code (MBM29DL34TF=2250h, MBM29DL34BF=2253h). Notice that the above applies to Word mode; the addresses and codes differ from those of Byte mode (Refer to "MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables" and "MBM29DL34TF/BF Extended Autoselect Code Tables" in s DEVICE BUS OPERATION.) . 5. Read Mode The device has two control functions required to obtain data at the outputs. CE is the power control and used for a device selection. OE is the output control and used to gate data to the output pins . Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, input hardware reset or to change CE pin from "H" or "L" 6. Output Disable With the OE input at a logic high level (VIH) , output from the devices are disabled. This will cause the output pins to be in a high impedance state. 7. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the device function. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever starts first. Standard microprocessor write timings are used. 8. Sector Group Protection The devices feature hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (See "Sector Group Addresses Tables (MBM29DL34TF/BF)" in s SECTOR-ERASE ARCHITECTURE) . The user's side can use the sector group protection using programming equipment. The device is shipped with all sector groups that are unprotected. To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL and A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. "Sector Address Tables (MBM29DL34TF/BF)" in s SECTOR-ERASE ARCHITECTURE define the sector address for each of the seventy one (71) individual sectors, and "Sector Group Addresses Tables (MBM29DL34TF/BF)" in s SECTOR-ERASE ARCHITECTURE define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See "15. Sector Group Protection Timing Diagram" in s TIMING DIAGRAM and "5. Sector Group Protection Algorithm" in s FLOW CHART for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 25 MBM29DL34TF/BF70 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logic "1" code at device output DQ0 for a protected sector. Otherwise the device will produce "0" for unprotected sector. In this mode, the lower order addresses, except for A6, A1, and A0 can be either High or Low. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on Byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logic "1" at DQ0 for a protected sector group. See "MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables" and "MBM29DL34TF/BF Extended Autoselect Code Tables" in s DEVICE BUS OPERATION for Autoselect codes. 9. Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to "16. Temporary Sector Group Unprotection Timing Diagram" in s TIMING DIAGRAM and "6. Temporary Sector Group Unprotection Algorithm" in s FLOW CHART. 10. Hardware RESET The devices may be reset by driving the RESET pin to VIL from VIH. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional "tRH" before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See "11. RESET, RY/BY Timing Diagram" in s TIMING DIAGRAM for the timing diagram. Refer to "9. Temporary Sector Group Unprotection" for additional functionality. 11. Byte/Word Configuration The BYTE pin selects the Byte (8-bit) mode or Word (16-bit) mode for the MBM29DL34TF/BF devices. When this pin is driven high, the devices operate in the Word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the devices operate in Byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer to "12. Timing Diagram for Word Mode Configuration", "13. Timing Diagram for Byte Mode Configuration" and "14. BYTE Timing Diagram for Write Operations" in s TIMING DIAGRAM for the timing diagram. 12. Boot Block Sector Protection The Write Protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two "outermost" 8 K byte boot sectors independently of whether those sectors were protected or unprotected using the method described in "Sector Group Protection". The two outermost 8 K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. (MBM29DL34TF : SA69 and SA70, MBM29DL34BF : SA0 and SA1) If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8 K byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two 26 MBM29DL34TF/BF70 sectors depends on whether they were last protected or unprotected using the method described in "Sector Group Protection". 13. Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed programming, so caution is needed as the sector group become temporarily unprotected. The system would use a fact program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See "18. Accelerated Program Timing Diagram" in s TIMING DIAGRAM. Erase operation at Acceleration mode is strictly prohibited. 27 MBM29DL34TF/BF70 s COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Some commands are required Bank Address (BA) input. When command sequences are inputted to bank being read, the commands have priority than reading. "MBM29DL34TF/BF Command Definitions Table" in s DEVICE BUS OPERATION defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Moreover both Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands must be asserted to DQ7 to DQ0 and DQ8 to DQ15 bits are ignored. 1. Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read mode, the Reset operation is initiated by writing the Reset command sequence into the command register. The device remains enabled for reads until the command register contents are altered. The device will automatically be in the reset state after power-up. In this case, a command sequence is not required to read data. 2. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. Therfore, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, applying high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. Following the command write, in Word mode, a read cycle from address (BA) 00h returns the manufacturer's code (Fujitsu = 04h) . A read cycle at address (BA) 01h outputs device code. Notice that the above applies to Word mode. The addresses and codes differ from those of Byte mode. (Refer to "MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables" and "MBM29DL34TF/BF Extended Autoselect Code Tables" in s DEVICE BUS OPERATION.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address (BA) 02h for x16 ( (BA) 04h for x8). Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logic "1" at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See "MBM29DL34TF/BF Sector Group Protection Verify Autoselect Codes Tables" and "MBM29DL34TF/BF Extended Autoselect Code Tables" in s DEVICE BUS OPERATION.) The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read. If the software (program code) for Autoselect command is stored into the Flash memory, the device and manufacture codes should be read from the other bank where is not contain the software. To terminate the operation, it is necessary to write the Reset command sequence into the register. To execute the Autoselect command during the operation, Reset command must be written before the Autoselect command. 3. Byte/Word Programming The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data 28 MBM29DL34TF/BF70 write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance. Hence, Data Polling requires the same address which is being programmed. If hardware reset occurs during the programming operation, the data being written is not guaranteed. Programming is allowed in any address sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may result in either failure condition or an apparent success according to the data polling algorithm. But a read from Reset mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Note that attempting to program a "1" over "0" will result in programming failure. This precaution is the same with Fujitsu standard NOR devices. "1. Embedded ProgramTM Algorithm" in s FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. 4. Program Suspend/Resume The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation immediately suspends the programming. The Program Suspend command can also be issued during a programming operation while an erase is suspended. The bank addresses of sector being programmed should be set when writing the Program Suspend command. When the Program Suspend command is written during a programming process, the device halts the program operation within 1 s and updates the status bits. After the program operation has been suspended, the system can read data from any address. The data at program-suspended address is not valid. Normal read timing and command definitions apply. After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses of sectors being suspended should be set when writing the Program Resume command. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system also writes Autoselect command sequence in the Program Suspend mode. The device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits from the Autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Program Resume command (address bits are "Bank Address") to exit from the Program Suspend mode and continue programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device resumes programming. 5. Chip Erase Chip erase is a six bus cycle operation. It begins two "unlock" write cycles followed by writing the "set-up" command, and two "unlock" write cycles followed by the chip erase command which is invokes the Embeded Erase algorithm. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm the devices will automatically program and verify the entire memory for an all zero data pattern prior 29 MBM29DL34TF/BF70 to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) ,DQ2 (Toggle Bit II ), or RY/BY output signal. The chip erase begins on the rising edge of the last CE or WE, whichever happens first from last command sequence and completes when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time = Sector Erase Time x All sectors + Chip Program Time (Preprogramming) "2. Embedded EraseTM Algorithm" in s FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 6. Sector Erase Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations. This sequence is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than Erase Time-out time (tTOW). Otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be reoccur after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector Erase command (s) . If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see "16. DQ3 Sector Erase Timer".) Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to "12. Write Operation Status" for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38) . Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector (s) to be erased prior to electrical erase using the Embedded Erase algorithm. When erasing a sector or sectors, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The sector erase begins after the "tTOW" time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and completes when the data on DQ7 is "1" (See "12. Write Operation Status".) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming) ] x Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform. "2. Embedded EraseTM Algorithm" in s FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 7. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform read or program to a sector not being erased. This command is applicable ONLY during the Sector Erase operation within the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being erasing or suspending should be set when writing the Erase Suspend or Erase Resume command. 30 MBM29DL34TF/BF70 When the Erase Suspend command is written during the Sector Erase operation, the devices take maximum of "tSPD" to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin will be at High-Z and the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See "17. DQ2".) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, it is the same as programming in the regular Program mode, except that the data must be programmed to sectors that are not erase-suspended. Reading successively from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 8. Extended Command (1) Fast Mode Set/Reset The device has Fast Mode function. It dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming consists of two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to "8. Embedded ProgramTM Algorithm for Fast Mode" in s FLOW CHART.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (Refer to "8. Embedded ProgramTM Algorithm for Fast Mode" in s FLOW CHART.) (3) Extended Sector Group Protection In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for the other addresses pins is recommended) , and write extended sector group protection command (60h) . A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h) . Following the command write, a logic "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logic "0", write extended sector group protection command (60h) again. To terminate the operation, set RESET pin to VIH. (Refer to "17. Extended Sector Group Protection Timing Diagram" in s TIMING DIAGRAM and "7. Extended Sector Group Protection Algorithm" in s FLOW CHART.) 31 MBM29DL34TF/BF70 (4) Query Command (CFI : Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to Common Flash memory Interface code. The operation is initiated by writing the query command (98h) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is "0" in Word mode (16 bit) read. Refer to the Common Flash memory Interface code table. To terminate operation, it is necessary to write the Reset command sequence into the register. (See "Common Flash Memory Interface Code Table" in s SECTOR-ERASE ARCHITECTURE.) 9. HiddenROM Region The HiddenROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 256 bytes in length and is stored at the same address of the 8 KB sectors. The MBM29DL34TF occupies the address of the byte mode 3FE000h to 3FE0FFh (word mode 1FF000h to 1FF07Fh) and the MBM29DL34BF type occupies the address of the byte mode 000000h to 0000FFh (word mode 000000h to 00007Fh) . After the system writes the Enter HiddenROM command sequence, it may read the HiddenROM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. 10. HiddenROM Entry Command The device has a HiddenROM area with one time protect function. This area is to enter the security code and to unable the change of the code once set. Programming is allowed in this area until it is protected. However, once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required. The HiddenROM area is 256 bytes. This area is normally the "outermost" 8 Kbyte boot block area in Bank 1. Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears. Sectors other than the boot block area SA0 can be read during HiddenROM mode. Read/program of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset command sequence. In HiddenROM mode, the simultaneous operation cannot be executed multi-function mode between the HiddenROM area and the Bank 1. 11. HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the usual program command, except that it needs to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data pooling, DQ6 toggle bit and RY/BY pin. You should pay attention to the address to be programmed. If an address not in the HiddenROM area is selected, the previous data will be deleted. 12. HiddenROM Protect Command There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command (60h) , set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the HiddenROM mode. The same command sequence may be used 32 MBM29DL34TF/BF70 because it is the same as the extension sector group protect in the past, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Please refer to "7. Extended Command (3) Extended Sector Group Protection" for details of extension sector group protect setting. The other method is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address in the HiddenROM area, and read. When "1" appears on DQ0, the protect setting is completed. "0" will appear on DQ0 if it is not protected. Apply write pulse again. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same as the sector group protect previously mentioned. Refer to "8. Secor Group Protection" in s FUNCTIONAL DESCRIPTION for details of the sector group protect setting. Take note that other sector groups will be affected if an address other than those for the HiddenROM area is selected for the sector group address, so please be careful. Pay close attention that once it is protected, protection CANNOT BE CANCELLED. 13. Write Operation Status Detailed in "Hardware Sequence Flags Table" are all the status flags that can determine the status of the bank for the current mode operation. The read operation from the bank that does not operate Embedded Algorithm returns a data of memory cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The information on DQ2 is address sensitive. If an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing. The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] In Progress Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode *1: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2: Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. 33 MBM29DL34TF/BF70 14. DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the devices will produce reverse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a "1" at the DQ7 output. The flow chart for Data Polling (DQ7) is shown in "3. Data Polling Algorithm" in s FLOW CHART. For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address of the sectors being erased, not protected sector. Otherwise, the status become invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 s, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See "Hardware Sequence Flags Table".) See "6. Data Polling during Embedded Algorithm Operation Timing Diagram" in s TIMING DIAGRAM for the Data Polling timing specifications and diagrams. 15. DQ6 Toggle Bit I The device also features the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the Toggle Bit will toggle for about 1 s and then stop toggling with the data unchanged. In erase, the devices will erase all the selected sectors except for the protected ones. If all selected sectors are protected, the chip will toggle the Toggle Bit for about 400 s and then drop back into read mode, having data kept remined. Either CE or OE toggling will cause the DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank is actively erasing (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause DQ6 to toggle. To operate Toggle bit function properly, CE or OE must be high when bank address is changed. See "7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram" in s TIMING DIAGRAM for the Toggle Bit I timing specifications and diagrams. 34 MBM29DL34TF/BF70 16. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in "MBM29DL34TF/BF User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" (s DEVICE BUS OPERATION). The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ5 bit will indicate a "1." Note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence. 17. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is high ("1") , the internally controlled erase cycle has begun. If DQ3 is low ("0") , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags Table". 18. DQ2 Toggle Bit II This Toggle Bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Toggle Bit Status Table" and "9. DQ2 vs. DQ6" in s TIMING DIAGRAM. Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate Toggle Bit function properly, CE or OE must be high when bank address is changed. 19. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading Toggle Bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a Toggle Bit is toggling. Typically a system would note and store the value of the Toggle Bit after the first read. After the second read, the system would compare the new value of the Toggle Bit with the first. If the Toggle Bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, after the initial two read cycles, if the system determines that the Toggle Bit is still toggling, the system also should note whether the value of DQ5 is high (see "15. DQ5") . If it is, the system should then determine 35 MBM29DL34TF/BF70 again whether the Toggle Bit is toggling, since the Toggle Bit may have stopped toggling just as DQ5 went high. If the Toggle Bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the Toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to "4. Toggle Bit Algorithm" in s FLOW CHART.) Toggle Bit Status Table DQ7 DQ7 0 1 DQ7 Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle *1 Toggle *1 1 *2 *1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. 20. RY/BY Ready/Busy The devices provide a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or erase operation. If the devices are placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to "10. RY/BY Timing Diagram during Program/Erase Operations" and "11. RESET, RY/BY Timing Diagram" in s TIMING DIAGRAM for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, the pull-up resistor needs to be connected to VCC ; multiple of devices may be connected to the host system via more than one RY/BY pin in parallel. 21. Data Protection The devices are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. 22. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min) . If Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is(are) not valid. 23. Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. 36 MBM29DL34TF/BF70 24. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logic zero while OE is a logic one. 25. Power-Up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 26. Sector Protection Device user is able to protect each sector group individually to store and protect data. Protection circuit voids both program and erase commands that are addressed to protected sectors. Any commands to program or erase addressed to protected sector are ignored. (See "8. Sector Group Protection" in s FUNCTIONAL DESCRIPTION.) 37 MBM29DL34TF/BF70 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET *1,*2 Power Supply Voltage *1 A9, OE, and RESET *1,*3 WP/ACC * * 1, 4 Symbol Tstg TA VIN, VOUT VCC VIN VACC Rating Min -55 -40 -0.5 -0.5 -0.5 -0.5 Max +125 +85 VCC + 0.5 +4.0 +13.0 +10.5 Unit C C V V V V *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *4 : Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when VCC is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperatuer Power Supply Voltage Symbol TA VCC Part No. MBM29DL34TF/BF 70 MBM29DL34TF/BF 70 Value Min -40 +2.7 Max +85 +3.6 Unit C V Notes: * Voltage is defined on the basis of VSS = GND = 0 V. * Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 38 MBM29DL34TF/BF70 s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.6 V -0.5 V -2.0 V 20 ns 20 ns 20 ns Maximum Undershoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC + 0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE, and RESET. Maximum Overshoot Waveform 2 39 MBM29DL34TF/BF70 s DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current Sym bol ILI ILO ILIT Conditions VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, f = 5 MHz CE = VIL, OE = VIH, f = 1 MHz CE = VIL, OE = VIH VCC = VCC Max, CE = VCC 0.3 V, RESET = VCC 0.3 V, WE/ACC = VCC 0.3 V VCC = VCC Max, RESET = VSS 0.3 V VCC = VCC Max, CE = VSS 0.3 V, RESET = VCC 0.3 V, VIN = VCC 0.3 V or VSS 0.3 V CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH VCC = VCC Max, WP/ACC = VACC Max IOL = 4.0 mA, VCC = VCC Min Byte Word Byte Word Byte Word Byte Word Value Min -1.0 -1.0 -0.5 2.0 8.5 11.5 2.4 VCC - 0.4 2.3 Typ 1 1 1 12 2.4 Max +1.0 +1.0 35 16 18 4 4 30 5 5 5 46 48 46 48 35 20 +0.6 VCC + 0.3 9.5 12.5 0.45 2.5 Uni t A A A mA mA mA A A A VCC Active Current * 1 ICC1 VCC Active Current *2 VCC Current (Standby) VCC Current (Standby, Reset) VCC Current (Automatic Sleep Mode) *3 VCC Active Current *5 (Read-While-Program) VCC Active Current *5 (Read-While-Erase) VCC Active Current (Erase-Suspend-Program) ACC Accelerated Program Current Input Low Level Input High Level Voltage for WP/ACC Sector Protection/ Unprotection and Program Acceleration Voltage for Autoselect and Sector Protection (A9, OE, RESET) *4 Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 IACC VIL VIH VACC VID VOL mA mA mA mA V V V V V V V V VOH1 IOH = -2.0 mA, VCC = VCC Min VOH2 IOH = -100 A VLKO *1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: Applicable for only VCC applying. *5: Embedded Algorithm (program or erase) is in progress (@5 MHz) . 40 MBM29DL34TF/BF70 s AC CHARACTERISTICS * Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time from Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE to BYTE Switching Low or High * : Test Conditions : Output Load : 1TTL gate and 100 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCC Timing measurement reference level Input : VCC / 2 Output : VCC / 2 tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Symbol JEDEC Standard Value * Test setup Min CE = VIL OE = VIL OE = VIL 70 0 tRC tACC tCE tOE tDF tDF tOH 70 Max 70 70 30 25 25 20 5 ns ns ns ns ns ns ns s ns Unit tREADY tELFL, tELFH 3.3 V Diode = 1N3064 or Equivalent 2.7 k Device Under Test 6.2 k CL Diode = 1N3064 or Equivalent Note : CL = 100 pF including jig capacitance Test Conditions 41 MBM29DL34TF/BF70 * Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling Symbol JEDEC Standard Min 70 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s ns ns s s s tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL Byte Word tWHWH1 tWHWH2 2 tWC tAS tASO tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP 70 0 12 45 0 30 0 0 10 20 20 0 0 0 0 0 0 35 35 25 25 50 500 500 4 100 4 4 6 0.5 CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Programming Operation Sector Erase Operation *1 VCC Setup Time Rise Time to VID * Rise Time to VACC *3 Voltage Transition Time *2 Write Pulse Width * 2 2 OE Setup Time to WE Active * (Continued) 42 MBM29DL34TF/BF70 (Continued) Parameter CE Setup Time to WE Active *2 Recover Time from RY/BY RESET Pulse Width RESET High Level Period before Read BYTE Switching Low to Output High-Z BYTE Switching High to Output Active Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-Out Time Erase Suspend Transition Time *1 : Does not include the preprogramming time. *2 : For Sector Group Protection operation. *3 : This timing is limited for Accelerated Program operation only. Symbol JEDEC Standard Min 70 Typ Max Unit 30 70 90 70 20 s ns ns ns ns ns ns ns s s tCSP tRB tRP tRH tFLQZ tFHQV tBUSY tEOE tTOW tSPD 4 0 500 200 50 43 MBM29DL34TF/BF70 s ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle Limits Min 100,000 Typ 0.5 6.0 4.0 Max 2.0 100 80 100 Unit s s s s cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Notes : * Typical Erase conditions TA = +25 C, Vcc = 2.9 V * Typical Program conditions TA = +25 C, Vcc = 2.9 V, Data = checker s TSOP (1) PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Condition Value Typ 6.0 8.5 8.0 9.0 Max 10.0 12.0 11.0 12.0 Unit pF pF pF pF Notes : * Test conditions TA = +25 C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance. s FBGA PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Condition Value Typ 6.0 8.5 8.0 9.0 Max 10.0 12.0 11.0 12.0 Unit pF pF pF pF Notes : * Test conditions TA = +25 C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance. 44 MBM29DL34TF/BF70 s TIMING DIAGRAM * Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L" Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Change from H to L Will Change from L to H Changing State Unknown Center Line is HighImpedance "Off" State 1. Read Operation Timing Diagram tRC Address tACC Address Stable CE tOE tDF OE tOEH WE tCE High-Z tOH High-Z Outputs Output Valid 45 MBM29DL34TF/BF70 2. Hardware Reset/Read Operation Timing Diagram tRC Address tACC Address Stable CE tRH tRP tRH tCE RESET tOH High-Z Outputs Output Valid 3. Alternate WE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling PA tAS tAH PA tRC Address 555h tWC CE tCS tCH tCE OE tGHWL tWP tWPH tOE tWHWH1 WE tDS tDH tDF tOH Data A0h PD DQ7 DOUT DOUT Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. * These waveforms are for the x16 mode (the addresses differ from x8 mode) . 46 MBM29DL34TF/BF70 4. Alternate CE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling PA tAS tAH PA Address 555h tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH PD DQ7 DOUT Data A0h Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. * These waveforms are for the x16 mode (the addresses differ from x8 mode) . 47 MBM29DL34TF/BF70 5. Chip/Sector Erase Operation Timing Diagram Address 555h tWC 2AAh tAS tAH 555h 555h 2AAh SA* CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh tDH 55h 80h AAh 55h 10h for Chip Erase 10h/ 30h Data tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word) , AAAh (Byte) for Chip Erase. Note : These waveforms are for the x16 mode (the addresses differ from x8 mode) . 48 MBM29DL34TF/BF70 6. Data Polling during Embedded Algorithm Operation Timing Diagram CE tCH tOE tDF OE tOEH WE tCE * DQ7 = Valid Data DQ7 Data DQ7 High-Z tWHWH1 or tWHWH2 DQ6 to DQ0 Data tBUSY DQ6 to DQ0 = Output Flag tEOE DQ6 to DQ0 Valid Data High-Z RY/BY * : DQ7 = Valid Data (the device has completed the Embedded operation.) 7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram Address tAHT tASO tAHT tAS CE tCEPH WE tOEH tOEPH tOEH OE tDH tOE Toggle Data tBUSY Toggle Data tCE Toggle Data * Stop Toggling Output Valid DQ6/DQ2 Data RY/BY * : DQ6 stops toggling (the device has completed the Embedded operation) . 49 MBM29DL34TF/BF70 8. Bank-to-Bank Read/Write Timing Diagram Read tRC Command tWC BA2 (555h) tAH Read tRC BA1 tACC tCE tAHT Command tWC BA2 (PA) Read tRC BA1 Read tRC BA2 (PA) tAS Address BA1 tAS CE tOE tCEPH OE tGHWL tWP tOEH tDF WE tDS Valid Output Valid Input (A0h) tDH tDF Valid Output Valid Input (PD) Valid Output DQ Status Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2 9. DQ2 vs. DQ6 Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE Erase Suspend Read DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CE Note : DQ2 is read from the erase-suspended sector. 50 MBM29DL34TF/BF70 10. RY/BY Timing Diagram during Program/Erase Operations CE Rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY 11. RESET, RY/BY Timing Diagram WE RESET tRP tRB RY/BY tREADY 12. Timing Diagram for Word Mode Configuration CE tCE BYTE DQ14 to DQ0 tELFH Data Output (DQ7 to DQ0) tFHQV A-1 DQ15 Data Output (DQ14 to DQ0) DQ15/A-1 51 MBM29DL34TF/BF70 13. Timing Diagram for Byte Mode Configuration CE BYTE DQ14 to DQ0 tELFL Data Output (DQ14 to DQ0) tACC Data Output (DQ14 to DQ0) DQ15/A-1 DQ15 tFLQZ A-1 14. BYTE Timing Diagram for Write Operations Falling edge of the last write signal CE or WE Input Valid tAH tAS BYTE 52 MBM29DL34TF/BF70 15. Sector Group Protection Timing Diagram A20, A19, A18 A17, A16, A15 A14, A13, A12 SGAX SGAY A6, A3, A2, A0 A1 VID VIH A9 VID VIH OE tVLHT tWPP tVLHT tVLHT tVLHT WE tOESP CE tCSP Data tVCS tOE 01h VCC SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected Note : A-1 is VIL on byte mode. 53 MBM29DL34TF/BF70 16. Temporary Sector Group Unprotection Timing Diagram VCC tVCS tVIDR tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection Period 54 MBM29DL34TF/BF70 17. Extended Sector Group Protection Timing Diagram VCC tVCS RESET tVIDR tVLHT tWC tWC SGAX SGAX SGAY Address A6, A3, A2, A0 A1 CE OE tWP TIME-OUT WE Data 60h 60h 40h tOE 01h 60h SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min) 55 MBM29DL34TF/BF70 18. Accelerated Program Timing Diagram VCC tVCS tVACCR tVLHT VACC VIH WP/ACC CE WE tVLHT tVLHT Program Command Sequence RY/BY Acceleration Period 56 MBM29DL34TF/BF70 s FLOW CHART 1. Embedded ProgramTM Algorithm EMBEDDED ALGORITHMS Start Write Program Command Sequence (See Below) Data Polling Device Embedded Program Algorithm in progress No Verify Data ? Yes Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command) : 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Notes : * The sequence is applied for x 16 mode. * The addresses differ from x 8 mode. 57 MBM29DL34TF/BF70 2. Embedded EraseTM Algorithm EMBEDDED ALGORITHMS Start Write Erase Command Sequence (See Below) Data Polling Embedded Erase Algorithm in progress No Data = FFh ? Yes Erasure Completed Chip Erase Command Sequence (Address/Command) : 555h/AAh Individual Sector/Multiple Sector Erase Command Sequence (Address/Command) : 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h Sector Address /30h Sector Address /30h Sector Address /30h 555h/10h Additional sector erase commands are optional. Notes : * The sequence is applied for x 16 mode. * The addresses differ from x 8 mode. 58 MBM29DL34TF/BF70 3. Data Polling Algorithm VA = Valid Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. Start Read Byte (DQ7 to DQ0) Addr. = VA Yes DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. 59 MBM29DL34TF/BF70 4. Toggle Bit Algorithm Start Read DQ7 to DQ0 Addr. = VA *1 VA = Bank address being executed Embedded Algorithm. Read DQ7 to DQ0 Addr. = VA *1 Toggle Bit = Toggle? Yes No DQ5 = 1? Yes No *1, *2 Read DQ7 to DQ0 Addr. = VA *1, *2 Read DQ7 to DQ0 Addr. = VA Toggle Bit = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command No Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether or not it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to "1". 60 MBM29DL34TF/BF70 5. Sector Group Protection Algorithm Start ( Setup Sector Group Addr. A20, A19, A18, A17,A16, A15, A14, A13, A12 PLSCNT = 1 ) OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = A3 = A2 = A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 s WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group Addr. = SGA, ( A6 = A3 = A2 =A1 ==VIH )* A0 VIL No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector Group ? No Device Failed Remove VID from A9 Write Reset Command Yes Sector Group Protection Completed * : A-1 is VIL in byte mode. 61 MBM29DL34TF/BF70 6. Temporary Sector Group Unprotection Algorithm Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1 : All protected sectors are unprotected. *2 : All previously protected sectors are reprotected. 62 MBM29DL34TF/BF70 7. Extended Sector Group Protection Algorithm Start RESET = VID Wait to 4 s Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Protect Secter Group Write 60h to Secter Address (A6 = A3 = A2 = A0 = VIL, A1 = VIH) Time out 250 s Increment PLSCNT To Verify Sector Group Protection Write 40h to Secter Address (A6 = A3 = A2 = A0 = VIL, A1 = VIH) Read from Sector Group Address (Addr. = SGA, A6 = A3 = A2 = A0 = VIL, A1 = VIH) No Data = 01h? Yes Protect Other Sector Group? No Remove VID from RESET Write Reset Command Yes No Setup Next Sector Address PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Device Failed Sector Protection Completed 63 MBM29DL34TF/BF70 8. Embedded ProgramTM Algorithm for Fast Mode FAST MODE ALGORITHM Start 555h/AAh 2AAh/55h Set Fast Mode 555h/20h XXXh/A0h Program Address/Program Data Data Polling In Fast Program Verify Data? Yes Increment Address No Last Address ? Yes Programming Completed No (BA) XXXh/90h Reset Fast Mode XXXh/F0h Notes : * The sequence is applied for x 16 mode. * The addresses differ from x 8 mode. 64 MBM29DL34TF/BF70 s ORDERING INFORMATION Part No. MBM29DL34TF70TN Package 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 48-pin plastic FBGA (BGA-48P-M12) 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 48-pin plastic FBGA (BGA-48P-M12) Access Time (ns) 70 Top Sector 70 Remarks MBM29DL34TF70PBT MBM29DL34BF70TN 70 Bottom Sector 70 MBM29DL34BF70PBT MBM29DL34 T F 70 TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Normal Bend PBT = Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29DL34 32 Mega-bit (4 M x 8-Bit or 2 M x 16-Bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 65 MBM29DL34TF/BF70 s PACKAGE DIMENSIONS 48-pin plastic TSOP (1) (FPT-48P-M19) Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. LEAD No. 1 48 INDEX Details of "A" part 0.25(.010) 0~8 0.600.15 (.024.006) 24 25 20.000.20 (.787.008) * 18.400.20 (.724.008) * 12.000.20 (.472.008) 1.10 -0.05 +0.10 +.004 .043 -.002 (Mounting height) 0.50(.020) "A" 0.10(.004) 0.17 -0.08 .007 -.003 C +0.03 +.001 0.100.05 (.004.002) (Stand off height) 0.220.05 (.009.002) 0.10(.004) M 2003 FUJITSU LIMITED F48029S-c-6-7 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 66 MBM29DL34TF/BF70 (Continued) 48-pin plastic FBGA (BGA-48P-M12) 9.000.20(.354.008) 1.05 -0.10 .041 -.004 (Mounting height) 0.380.10(.015.004) (Stand off) +0.15 +.006 5.60(.220) 0.80(.031)TYP 6 5 INDEX 6.000.20 (.236.008) 4 4.00(.157) 3 2 1 H C0.25(.010) G F E D C B A M 48-o0.450.10 (48-o.018.004) o0.08(.003) 0.10(.004) C 2001 FUJITSU LIMITED B48012S-c-3-3 Dimensions in mm (inches) Note : The values in parentheses are reference values. 67 MBM29DL34TF/BF70 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0311 (c) FUJITSU LIMITED Printed in Japan |
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